1. Field of the Invention
This invention relates to a method for the production of a semiconductor integrated circuit device and more particularly to a method for the production of a semiconductor integrated circuit device provided with a high voltage MOS transistor, which method is characterized by allaying the leak current consequent on the high voltage MOS transistor and, at the same time, stabilizing the characteristics of the MOS transistor of an LDD (light doped drain) structure.
2. Description of the Prior Art
The semiconductor integrated circuit devices which are provided with a high voltage MOS transistor have been heretofore used in the field of drivers for operating such microcomputers and liquid crystal panels as incorporate therein an FLT (fluorescent light tube) driver. The targets, viz exaltation of voltage difference between two terminals and miniaturization, that are set for the transistors primarily are physically irreconcilable requirements. The development of the semiconductor integrated circuit devices of this class, therefore, incurs various technical problems. One of these problems concerns the leak current which occurs when the device adopting the MOS transistor of the so-called LDD structure for the sake of miniaturization is in the turn OFF state. This problem will be explained below with reference to FIGS. 1.about.5.
With reference to FIG. 1, a P well 32 is formed on an N type Si substrate 31 and a field oxide film 33 is formed in areas requiring element separation such as, for example, the boundary between the P well 32 and the N type Si substrate 31.
The periphery of the P well 32 is surrounded by the field oxide film 33 and a gate insulating film 34B is formed on the surface of the P well 32. A gate electrode 35B is formed on the gate insulating film 34B. In the surface layer of the P well 32, an N.sup.- type source layer 37 and an N.sup.- type drain layer 38 are formed by ion implantation as opposed to each other across the gate electrode 35B.
Further, the field oxide film 33 is formed on the surface of the N type Si substrate 31 in which the P well 32 is not formed, a gate insulating film 34A is formed on the surface of the active area surrounded by the field oxide film 33, and a gate electrode 35A is formed on the surface of the gate insulating film 35A as shown in FIG. 1.
Further, a P.sup.- drain layer 36 is formed on the surface of the N type Si substrate 31 falling on one side of the gate electrode 35A. A CVD oxide film 39 is formed so as to cover all the surfaces formed consequently.
The CVD oxide film 39 in the ensuing state is etched without the resist covered area thereof by anisotropic etching such as, for example, the RIE (reactive ion etching) to form lateral wall spacer films 40 one each on the lateral walls of the gate electrodes 35A, 35B as shown in FIG. 2. During the process of this etching, the surface of the Si substrate is etched over and damage layers 41 containing such faults as a crystal defect are formed on the etched surfaces by the impact of ions which are etching species.
Then, by selectively injecting a P.sup.+ type impurity atoms, a P.sup.+ type source region 42 is formed on the surface of the N type Si substrate 31 opposite the P.sup.- drain region 36 across the gate electrode 35A and, at the same time, a P.sup.+ type drain region 43 is formed in the surface region of the P.sup.- drain region 36 as shown in FIG. 3. Subsequently, by selectively introducing an N.sup.+ type impurity atoms, an N.sup.+ type source region 44 and an N.sup.+ type drain region 45 are formed on the P wells 32 on the opposite sides of the gate electrode 35B.
In consequence of the process described above, a P channel high voltage MOS transistor is formed on the surface of the N type Si substrate 31 and an N channel MOS transistor (normal voltage MOS transistor) is formed on the surface of the P well 32.
Incidentally, it has been confirmed that in the high voltage MOS transistor formed in consequence of the process described above, a damage layer 41A to be formed on the surface of the P.sup.- type drain layer 36 induces occurrence of a leak current from the P.sup.- type drain layer 36 to the N type Si substrate 31.
The occurrence of this leak current may be logically explained by a supposition that when a high voltage is applied to the drain of the high voltage MOS transistor, the P.sup.- type drain region 36 undergoes depletion of carriers and the depletion region widens as far as the damage layer 41A in the proximity of the gate electrode and, as a result, the generation current occurred by recombination-generation centers due to the crystal defect inevitably flows from the damage layers 41 to the N type Si substrate 31.
For the purpose of preventing this leak current, the present inventors have tried a procedure which comprises performing isotropic etching such as, for example, the wet etching which causes etching damage only sparingly and thereby forming the lateral wall spacer films 40 and subsequently removing the damage layers 41 as shown in FIG. 4 and thereafter forming the P.sup.+ type source layer 42, the P.sup.+ type drain layer 43, an N.sup.+ type source layer 44, and an N.sup.+ type drain layer 45 as shown in FIG. 5.
This procedure has resulted in removing the damage layers and, as a result, allaying the leak current mentioned above. Since the isotropic etching allows only poor control of the amounts of Si side-etching, however, it entrains such disadvantages as rendering ununiform the intervals (a) between the adjacent edges formed as shown in FIG. 4 by the etching and consequently impairing the constancy of the transistor characteristics like the ON resistance.
Incidentally, when the removal of the damage layer 41 of Si surface is effected by anisotropic etching, the work of etching can be carried out as critical dimension controlled without entraining such poor control of the amount as side etching. The anisotropic etching does not allow perfect prevention of the leak current, however, because it gives rise to damage layers again.
Further, a procedure which comprises forming the gate electrodes 35A, 35B with polysilicon and thereafter performing a thermal oxidation and thereby forming a relatively thick oxide film on the P.sup.- type drain layer 36 and consequently preventing the P.sup.- type drain layer 36 from being exposed during the subsequent course of anisotropic etching is conceivable.
When the gates are formed of polysilicon, however, they are at a disadvantage in hampering any effort to exalt the operating speed of a device because the polysilicon layers offer such a relatively high resistance as falls in the neighborhood of 30 .OMEGA./.quadrature.. The adoption of a polycide gate structure, namely a two-layer structure of tungsten and polysilicon, which offers low resistance in the approximate range of 8.about.10 .OMEGA./.quadrature. as compared with the polysilicon gates, therefore, has been tried. The adoption of this structure, however, entrains the problem that a tungsten polycide layer peels from the polysilicon layer during the course of thermal oxidation of the two-layer structure. Therefore, the polycide structure can not be used the thermal oxidation.